1. Field
Various embodiments of the present invention relate to the manufacturing of semiconductors and multi-layer reticles, and, more particularly, to structures that can indicate parameters of the semiconductor or reticle workpieces.
2. Description of the Related Art
Semiconductor devices and reticles are generally formed by repeating the steps of providing a layer, forming a pattern over the layer, removing the material not covered by the pattern, and removing the pattern. Multiple patterned layers can thereby be formed. For example, as semiconductor device dimensions are reduced, for example to increase device density or to increase device speed, accurate pattern formation becomes increasingly important. Patterned layers that are misaligned with respect to other patterned layers or that are incorrectly sized can lead to devices that do not function properly or fail. Measurement of certain parameters of a patterned layer and adjustment of the patterning process based on such measurements can aid in the formation of patterns that are properly aligned and sized. In particular, measurement of the “overlay” (e.g., how well one pattern is aligned with an underlying pattern or patterns) and the “critical dimensions” (e.g., the sizes of particular features) can verify the accurate formation of patterns.
As the dimensions of devices on workpiece shrink, accurate measurement of overlay and critical dimensions becomes increasingly difficult and necessitates the development of new techniques. For example, some critical dimensions may be on the order of tens of nanometers, thereby requiring non-optical tools such as a scanning electron microscope for measurement.